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| UVM Methodology |
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UVM Methodology, Duration: 2 months
The course covers the following modules. UVM Methodology + Project
(Prior knowledge on System Verilog is must for this)
• Introduction to UVM
• Phasing
• Reporting
• UVM TB Architecture
• UVM Class Library, Macros, Utilities
• UVM Factory, Synchronization
• Transactions
• UVM Components, Sequences, Sequencer, Driver, Monitor, Agent
• Coverage Monitor, Scoreboard
• Stimulus Modeling, Sequences & Sequencers
• Virtual Sequences and Virtual Sequencer
• Creating UVCs and Environment
• UVM Simulation Phases
• TLM Overview, Components
• Configuring TB Environment
• Register Layer, Configuration db & Resource db
• Connecting multiple UVCs
• Test classes
• Creating TB in UVM
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