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| System Verilog |
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System Verilog, Duration: 2 months
The course covers the following modules. System Verilog + Project
• Introduction to Verification
• Introduction to Verification Plan and Test Plan
• Verification Tools
• Evolution of System Verilog
• New Additions to System Verilog
• New features
• Importance of Functional verification in Chip design
• Introduction to BFMs, Verification environment and its components
• System Verilog Basics - Introduction to System Verilog, Enhancement in System Verilog, Interface and Modports
• System Verilog for Verification - System Verilog Event Ordering
• Clocking block and Program block, OOP's Concept of System Verilog - Parameterized classes, Virtual interface, Constrained Randomization techniques, Functional Coverage
• Encapsulation
• Randomization
• Inheritance & Polymorphism
• Callbacks
• DPI
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