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| Advanced Design & ASIC Verification |
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Advanced Design & ASIC Verification, Duration: 5 months
The course covers the following modules.
» Linux Basics
» Digital Design Concepts
• Number Systems, Combinational Logic Design
• Logic gates
• Designing with Mux, Demux, Decoders, Encoders
• Sequential Logic Design- D Latch, D Flop
• Design of Sequential Systems - Registers and Counters
• Synchronous Finite State Machine Design
• Data-path elements - Arithmetic Structures
• Introduction to and Programmable Platforms
• Design Capture and Simulation
» Verilog + Mini Project on Design
• Evolution of Hardware Description Languages
• Hardware Modeling Overview
• Verilog language concepts
• Modules and Ports
• Dataflow Modeling
• Operators
• Data types
• Introduction to Test benches
• Operators & Procedural Statements
• Control Statements
• Hardware modeling - Structural, Dataflow and Behavioral
• Coding for Finite State Machines
• Coding for Synthesis
• Tasks and Functions
• Advanced Verilog Test benches
• Importance of functional verification
• Verilog constructs for functional verification
• System tasks
• File I/O Operations
• Compiler directives
» System Verilog + Mini Project on Verification with SV
• Introduction to Verification
• Introduction to Verification Plan and Test Plan
• Verification Tools
• Evolution of System Verilog
• New Additions to System Verilog
• New features
• Importance of Functional verification in Chip design
• Introduction to BFMs, Verification environment and its components
• System Verilog Basics - Introduction to System Verilog, Enhancement in System Verilog, Interface and Modports
• System Verilog for Verification - System Verilog Event Ordering
• Clocking block and Program block, OOP's Concept of System Verilog - Parameterized classes, Virtual interface, Constrained Randomization techniques, Functional Coverage
• Encapsulation
• Randomization
• Inheritance & Polymorphism
• Callbacks
• DPI
» UVM Methodology + Project on Verification with UVM
• Introduction to UVM
• Phasing
• Reporting
• UVM TB Architecture
• UVM Class Library, Macros, Utilities
• UVM Factory, Synchronization
• Transactions
• UVM Components, Sequences, Sequencer, Driver, Monitor, Agent
• Coverage Monitor, Scoreboard
• Stimulus Modeling, Sequences & Sequencers
• Virtual Sequences and Virtual Sequencer
• Creating UVCs and Environment
• UVM Simulation Phases
• TLM Overview, Components
• Configuring TB Environment
• Register Layer, Configuration db & Resource db
• Connecting multiple UVCs
• Test classes
• Creating TB in UVM
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